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AT24HC02B
7. Write Operations
BYTE WRITE: A write operation requires an 8-bit data word address following the device
address word and acknowledgement. Upon receipt of this address, the EEPROM will again
respond with a “0” and then clock in the first 8-bit data word. Following receipt of the 8-bit data
word, the EEPROM will output a “0” and the addressing device, such as a microcontroller, must
terminate the write sequence with a stop condition. At this time, the EEPROM enters an inter-
nally-timed write cycle, t WR , to the nonvolatile memory. All inputs are disabled during this write
cycle, and the EEPROM will not respond until the write is complete, see Figure 7-1 on page 9 .
Figure 7-1.
Byte Write
S
T
A
R
T
DEVICE
ADDRESS
W
R
I
T
E
WORD ADDRESS
DATA
S
T
O
P
SDA LINE
M
S
B
R A
/ C
W K
A
C
K
A
C
K
PAGE WRITE: The 2K EEPROM is capable of an 8-byte page write.
A page write is initiated the same as a byte write, but the microcontroller does not send a stop
condition after the first data word is clocked in. Instead, after the EEPROM acknowledges
receipt of the first data word, the microcontroller can transmit up to seven (2K) more data words.
The EEPROM will respond with a “0” after each data word received. The microcontroller must
terminate the page write sequence with a stop condition, see Figure 7-2 .
Figure 7-2.
Page Write
S
T
A
R
T
DEVICE
ADDRESS
W
R
I
T
E
WORD ADDRESS (n)
DATA (n)
DATA (n + 1)
DATA (n + x)
S
T
O
P
SDA LINE
M
S
B
R A
/ C
W K
A
C
K
A
C
K
A
C
K
A
C
K
The data word address lower three (2K) bits are internally incremented following the receipt of
each data word. The higher data word address bits are not incremented, retaining the memory
page row location. When the word address, internally generated, reaches the page boundary,
the following byte is placed at the beginning of the same page. If more than eight (2K) data
words are transmitted to the EEPROM, the data word address will “roll over” and previous data
will be overwritten.
ACKNOWLEDGE POLLING: Once the internally-timed write cycle has started and the
EEPROM inputs are disabled, acknowledge polling can be initiated. This involves sending a
start condition followed by the device address word. The read/write bit is representative of the
operation desired. Only if the internal write cycle has completed will the EEPROM respond with
a “0” allowing the read or write sequence to continue.
9
5134E–SEEPR–3/08
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